The present invention relates to semiconductor device manufacturing, in particular, to a method of silicidizing silicon-containing areas in the array region of a dynamic random access memory (DRAM) or embedded DRAM (eDRAM) device to lower electrical resistance and to improve device reliability at low temperatures.
In semiconductor integrated circuits, the reliable operation of the devices therein depends heavily upon the passage of electrical currents through interconnected pathways in the devices. In these circuits, since current flow is directly related to resistance, the lower the resistance, the better the operation.
Further, in these devices, an important performance requirement is reliable operation at low temperatures. Thus, for instance, DRAM modules intended to operate at 0xc2x0 C. must pass a xe2x88x9210xc2x0 C. test in order to reduce the likelihood of device failure. Similarly, for eDRAM modules wherein a part of the module is embedded in the semiconductor structure, an even more severe test at xe2x88x9240xc2x0 C. has been suggested.
One problem that complicates the fabrication of semiconductor devices having low resistance and high reliability at low temperatures, is the observation that as the temperature is lowered, the resistance of the silicon increases. Thus, in DRAM and eDRAM devices that rely on doped silicon structures to provide the passage of electrical charge, the resistance increases and array functionality decreases as the operating temperature is lowered.
Insofar as eDRAMs are concerned, the buried strap is a conductive pathway in an eDRAM device located between the active silicon on the drain side of the field effect transistor (FET) and the trench capacitor. The buried strap facilitates charges to be written to, or read from, the capacitor and comprises a highly doped portion of the substrate. Physically, the buried strap is approximately 100 nm thick, extends across the pathway, and is buried approximately 50 nm below the surface of the substrate.
In the art, it is known to use various approaches to reduce resistance and improve reliability at lower temperatures. For example, designers have implemented shorter pathways in conjunction with utilizing highly conductive metals, and/or highly doped areas of the substrate, and/or highly conducting silicides, notably, the silicides of cobalt, nickel and titanium.
In this regard, silicides are conventionally formed in self-aligned processes, whereby a metal film is deposited over the silicon-containing region to be silicidized. The process involves in-situ cleaning of the silicon-containing region, followed by deposition of a metal on the silicon-containing region by means well known in the art. Thereafter, the structure is annealed by heating to form the silicide. Any unreacted metal that is not silicided may be removed by a selective wet etching process to remove metal without attacking the silicide. In DRAM and eDRAM devices, silicides may be found in the drain region, bitline contact, wordline and interconnecting pathways.
In the art, silicidizing silicon-containing regions has achieved success in reducing resistance and improving functionality at low operating temperatures, however, notwithstanding the success, it has become evident that DRAM yields are affected by: a) excessive node junction leakage due to the presence of the silicide; and b) silicide agglomeration on the wordline and in the active area. As a result, current DRAM and eDRAM manufacturing processes have steered completely away from silicidizing the pathways and structures. Consequently, the only silicide seen is these structures is a polycided wordline i.e., gate conductor, comprising tungsten silicide on a highly doped polysilicon.
Since silicides offer the potential for low resistance and reliable operation at low temperature, it is desirable to continue to utilize silicides in memory structures, but without the prior art problems.
Accordingly, it is desirable to provide a method of forming silicides in silicon-containing regions in the array device regions of a memory device whereby the problems of excessive node junction leakage and silicide agglomeration are minimized or eliminated, while providing for better conduction and improved reliability.
It is also desirable to provide a method of siliciding silicon-containing areas in the array device regions of DRAMs and eDRAMs to lower resistance and improve low temperature reliability.
In view of the foregoing, it is an object of the present invention to provide a method of silicidizing silicon-containing areas in the array regions of memory devices to lower the electrical resistance thereof.
It is also an object of the invention to provide a method of fabricating DRAM and eDRAM devices wherein the resistance of the buried strap, the wordline, the bitline contact and the drain region and abutting areas is lowered.
These and other objects are achieved in the present invention by utilizing a method of silicidizing silicon-containing areas in the array region of a memory devices to lower electrical resistance thereof. Specifically, the method of the present invention comprises the steps of:
a) applying a resist and a block-level mask to lithographically define an array region of a memory device;
b) doping said array region of said memory device so as to form a graded junction therein;
c) removing said resist;
d) annealing said array region;
e) etching said array region of said memory device so as to remove any native oxides from surfaces of said array region;
f) depositing a layer of conductive metal on said array region;
g) forming a capping layer on said conductive metal layer;
h) rapidly annealing said array region at a temperature less than about 600xc2x0 C.;
i) removing said capping layer and any residual conductive metal from said array region;
j) rapidly annealing said array region at a temperature of about 700xc2x0 C. or above; and
k) depositing an oxide layer on said array region.
Also provided in accordance with an object of the present invention is a method wherein an electrical pathway connecting the bitline contact of an eDRAM device with a capacitor device of the said eDRAM memory cell is silicidized for lowered resistance and improved low temperature operation.
Step b) of the present invention which forms a deep and graded junction underneath the silicide is carried out utilizing a xe2x80x9cmedium-highxe2x80x9d dose of phosphorous (dose greater than 2E13) and a xe2x80x9cmediumxe2x80x9d implant energy (25-60 KeV). The formation of the deep, graded junction in the array device region prior to silicidation reduces leakage next to the node junction as well as resistance in the pathways.